Re: Do I need to connect all Vref in a bank together?

Jan Panteltje wrote:
> 
> On a sunny day (Mon, 17 Nov 2003 07:39:03 -0800) it happened Austin Lesea
> <[EMAIL PROTECTED]> wrote in <[EMAIL PROTECTED]>:
> 
> >Jan,
> >
> >Yes, they are all internally connected on the die (once the IOB is programmed
> >as a Vref).
> That explains why I measure OC with an Ohm meter.
> 
> >Since these are also general purpose IOBs, there is no bypass cap in the
> >package, nor on the internal Vref line, so all external Vref pins must be
> >externally individually bypassed to ground with bypass caps as close as
> >possible to the Vref pins AND connected to the Vref supply to get the lowest
> >noise Vref possible.
> hehe, I am using Vref as video input, trying to use the thing as AD.
> On the other input of the comparator is an r2r ladder.
> The verilog does successive approximation.
> I ran into problems because indeed now Vref is 75 Ohm impedance to ground,
> and this pin is very sensitive.
> Connecting all Vrefs makes little difference.
> But I do have video (via second r2r ladder out again), but some spikes are at
> some places for example if you put in a sine wave.
> Seems I will have to sample and hold first too...
> Still some instability in that input comparator, if sh does not fix it I will
> try using external comparator.
> Also it works to digitize audio it seems.
> It is just for play....

 You could also try a Tracking ADC, rather than SAR - SAR is sensitive
to
noise, and have 'noise gain' which means large OP impulse errors can
come from small IP errors. (which is what you are seeing) 
 Tracking ADCs are better behaved, and would suit the faster speed / 
but not analog-optimised resource in the FPGA.

 - jg