Re: Newbie Question about Block Ram & Xilinx ECS

"Phil Hays" <[EMAIL PROTECTED]> wrote in message
news:[EMAIL PROTECTED]
> I don't use ISE schematic entry, but the error messages are familiar.  It
looks
> very much like the schematic is being translated to VHDL for simulation.
The
> messages are the same I would get if I didn't have all connections to a
lower level
> block made.  Is it possible that you don't have all pins of this
RAMB4_S16_S16
> connected?
>
> If you understand VHDL at all, you might want to look at the TopLevel.vhf
file
> with a text editor and see what is going on.
>
>
> -- 
> Phil Hays

Hi Phil, thanks for the reply.

I dont need some of the connections, so you correctly speculated about the
connections, but I have tried making dummy connections but I still get the
same error messages :( I will have to get to grips with
HDL sooner than expected ...

Thanks, Martin