Re: Do I need to connect all Vref in a bank together?

Jan Panteltje wrote:
> Spartan 2 datasheet says Vrefs are internally connected, but must also be
> externally connected.
> Is this really needed if you only use one input?

Howdy Jan,

The wording about Vrefs is a little awkward.  When they say they are 
"internally connected", they do not necessarily mean "internally 
connected TOGETHER".  I believe you only need to connect to the Vrefs on 
the bank with your single input.

Here is a quote from the Xilinx web site:
<<Some of the I/O standards require VCCO and/or VREF voltages. These 
voltages externally are connected to device pins that serve groups of 
IOBs, called banks. Consequently, restrictions exist about which I/O 
standards can be combined within a given bank. Eight I/O banks result 
from separating each edge of the FPGA into two banks. Each bank has 
multiple VCCO pins, all of which must be connected to the same voltage. 
This voltage is determined by the output standards in use.

In TQ144 and PQ208 packages, all VCCO pins are bonded together 
internally, and consequently the same VCCO voltage must be connected to 
all of them. In the CS144 package, bank pairs that share a side are 
interconnected internally, permitting four choices for VCCO. In both 
cases, the VREF pins remain internally connected as eight independent 
banks.>>

As you can see, they qualify the term "internally connected" with "eight 
independent banks."  Hence, the "internally connected" indicates that 
the lines are connected to the die, not that all the Vrefs of the device 
are tied together.

Have fun,

   Marc