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> The SRAM I'm thinking of using is Cypress, will be running it at > 150+Mhz, and the device supports these JTAG instructions : EXTEST, > IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported, > actually). Are the SRAM read control signals connected to the FPGA? If not, I think you will need to use INTEST instruction, but looks like the SRAM does not support it. Jim Wu [EMAIL PROTECTED] (remove capital letters) http://www.geocities.com/jimwu88/chips
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