Comp Post Archive from Usenet.com

www.Usenet.com

Group Index

__Thread Index__ [__Earlier messages__] [__Later messages__]

Comp Thread Archive from Usenet.com

Re: Digilent Inc.
- __From__: Jan Panteltje <12/02/2003>
Re: Digilent Inc.
- __From__: Alex Gibson <12/02/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Yttrium <12/02/2003>
Digilent Inc.
- __From__: GN <12/02/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Martin Euredjian <12/02/2003>
Re: 5V I/O with 1.8V Core
- __From__: Nicholas C. Weaver <12/02/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Yttrium <12/02/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Yttrium <12/02/2003>
Re: problem with RS485 or RS232
- __From__: MARTIN jm <12/02/2003>
how to create timing report for all nets?
- __From__: Alfredo <12/02/2003>
problem with RS485 or RS232
- __From__: Davide Canina <12/01/2003>
Re: area constraints
- __From__: A.y <12/01/2003>
Timing Analyzer - delay to die pad or package pin?
- __From__: Allan Herriman <12/01/2003>
Re: Any integesting article about PLD for short presentation
- __From__: valentin tihomirov <12/01/2003>
Re: graphic card accelarator vs. FPGA: which is better for the following task?
- __From__: walala <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: walala <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: walala <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Jim Granville <12/01/2003>
Re: Any integesting article about PLD for short presentation
- __From__: MM <12/01/2003>
Re: PCI LogiCORE with ISE 5.2
- __From__: Mark van de Belt <12/01/2003>
Re: Dual port RAM for Xilinx
- __From__: Mark van de Belt <12/01/2003>
[RFC] FPGA in AGP x8 slot?
- __From__: Roger Larsson <12/01/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Martin Euredjian <12/01/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Marc Randolph <12/01/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: John_H <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Nicholas C. Weaver <12/01/2003>
Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Martin Euredjian <12/01/2003>
Re: area constraints
- __From__: Martin Euredjian <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Hal Murray <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Nicholas C. Weaver <12/01/2003>
[VirtexII + DCM + newbie] problems with the clocksignals from DCM
- __From__: Yttrium <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: Paul Hartke <12/01/2003>
Any integesting article about PLD for short presentation
- __From__: valentin tihomirov <12/01/2003>
modular design flow in Xilinx ISE 6.1.
- __From__: Ian <12/01/2003>
Re: Slightly unmatched UART frequencies
- __From__: Watt Sun, Dark Remover <12/01/2003>
Re: IDE Ultra DMA on a SPARTAN II
- __From__: nomanland <12/01/2003>
Re: external sdram and gdb tool
- __From__: Tom <12/01/2003>
Re: external sdram and gdb tool
- __From__: Tom <12/01/2003>
Re: XC9500 design does not fit into Coolrunner
- __From__: Iwo Mergler <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: Kolja Sulimma <12/01/2003>
Re: area constraints
- __From__: A.y <12/01/2003>
Re: Slightly unmatched UART frequencies
- __From__: glen herrmannsfeldt <12/01/2003>
Re: overshoot problem of EPM7128S
- __From__: Krzysztof Szczepanski <12/01/2003>
Re: DDFS technique problem in generating a few clocks
- __From__: Allan Herriman <12/01/2003>
DDFS technique problem in generating a few clocks
- __From__: praveen <12/01/2003>
Re: Slightly unmatched UART frequencies
- __From__: Jean Nicolle <12/01/2003>
Re: Infer DDR registers from RTL?
- __From__: praveen <12/01/2003>
Re: Reverse engineering an EDIF file?
- __From__: Muthu <12/01/2003>
Re: Input pins without Vcco supply-- Virtex-II
- __From__: Jay <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: Muthu <12/01/2003>
Re: Affordable Development Board
- __From__: Vaughn Betz <12/01/2003>
Xilinx FPGA Clock Skew
- __From__: Muthu <12/01/2003>
Re: How many dedicated clock pins EP20K1500EBC652 device?
- __From__: Vaughn Betz <12/01/2003>
PCI LogiCORE with ISE 5.2
- __From__: Dean Armstrong <12/01/2003>
overshoot problem of EPM7128S
- __From__: Jian Ju <12/01/2003>
Re: Xilinx ISE 6.1 external editor
- __From__: Peng Cong <12/01/2003>
Re: XC9500 design does not fit into Coolrunner
- __From__: Robert Sefton <12/01/2003>
Phy IP for Giga ethernet for Virtex -II Pro
- __From__: Anup Raghavan <12/01/2003>
Xilinx ISE 6.1 external editor
- __From__: Gavin Melville <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Jim Granville <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Peter Alfke <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: walala <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: John Williams <12/01/2003>
Re: Soft-core processor construction
- __From__: Sumit Gupta <12/01/2003>
Re: Where and How to get Nvidia Geforce 5600 public desigh graph
- __From__: Ken Ryan <12/01/2003>
Re: what is the fastest speed that FPGA deals with CPU?
- __From__: Kolja Sulimma <12/01/2003>
Re: IDE Ultra DMA on a SPARTAN II
- __From__: steven derrien <12/01/2003>
IDE Ultra DMA on a SPARTAN II (corrected version)
- __From__: steven derrien <12/01/2003>
Re: Slightly unmatched UART frequencies
- __From__: Ulf Samuelsson <12/01/2003>
Re: IDE Ultra DMA on a SPARTAN II
- __From__: noone <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Peter Alfke <12/01/2003>
Re: running from external memory (microblaze)
- __From__: mohan <12/01/2003>
Re: Slightly unmatched UART frequencies
- __From__: Philip Freidin <12/01/2003>
Re: Reverse engineering an EDIF file?
- __From__: Frank Raffaeli <12/01/2003>
Re: area constraints
- __From__: Steve Lass <12/01/2003>
Re: external sdram and gdb tool
- __From__: Ryan Laity <12/01/2003>
Re: Xilinx Microblaze SDRAM burst access
- __From__: steven derrien <12/01/2003>
IDE Ultra DMA on a SPARTAN II
- __From__: steven derrien <12/01/2003>
Re: running from external memory (microblaze)
- __From__: Frank <12/01/2003>
Re: Input pins without Vcco supply-- Virtex-II
- __From__: Austin Lesea <12/01/2003>
Re: How many dedicated clock pins EP20K1500EBC652 device?
- __From__: enq_semi <12/01/2003>
Re: 5V I/O with 1.8V Core
- __From__: Austin Lesea <12/01/2003>
FS: Vitex-II / APEX20K
- __From__: Emile <12/01/2003>
Re: graphic card accelarator vs. FPGA: which is better for the following task?
- __From__: Kolja Sulimma <12/01/2003>
Re: getting started in FPGA
- __From__: Vaughn Betz <12/01/2003>

[__Earlier messages__] [__Later messages__]

Please check out one of the premium Usenet Newsgroup Service Providers below for access to Usenet.