I'm not sure, if this is off topic, but I'll try :)
I'm looking for an error detection method for hardware multipliers. I
found a paper describing parity prediction but this seems to be large
overhead and I'm trying to keep the overhead as small as possible.
I also found a paper that sais: take the self-dual complement of a
funcion (multiplication), XOR the results, if the output constantly
changes everything is allright. But in this case I have to have the
functional description of every output bit of, in my case, a 32 bit
multiplier to generate the self-dual complement - I don't have that.
Any ideas?
I don't want to detect single faults - if an error occurs, it will occur
forever.
Cheers,
Tom
How to detect errors in a multiplier,
Thomas Gutzler